The New V3 Graphics Board

To condense the discrete logic of my graphics system onto a single PCB I used three CPLDs - flash programmable chips that can take on the function of x number of logic gates. Ideally the entire glue logic of the graphics system would go on one chip but there were too many gates to fit in the kind of CPLD I was using, ie: affordable, PLCC socket types. (There are of course FPGAs which would hold the entire project - but they have many additonal complexities and I was taking it a step at a time and using CPLDs)

When deciding how to spread the logic over the three CPLDs, I largely stuck to the way the functions were arranged across the PCBs of the V2 system. Having said that, most of the actual logic was totally redesigned. The biggest change was the removal of the 2nd parallel display buffer from the original design - its original purpose was to allow the CPU to read/write a display buffer at full speed all the time (a bit like dual-ported RAM) - however it was cumbersome, doubled up a lot of logic and didnt really justify itself in terms of performance gain, so I ditched it.

Anyway, here's a run down of the functions assigned to the CPLDs (the actual schematics can be found in the file base)..

CPLD #1 XC95108 - Handles switching the address bus of the video ram SRAM between the CPU and the video system. Also contains the address counter for the video system (which now has two modes of operation for bitmap and character map modes) and the planar-to-chunky pixel converter. Interfaces with SX28 which organises pixel datafetch.

CPLD #2 XC95108 - Is the main interface to the Z80, contains the video registers and memory address range decoding. Has logic to generate the video frame timing (this is new in the V3 system, previously the TV frame was handled by a SX28 microcontroller).

CPLD #3 XC9572 - Sprite and Palette control. Switches address bus of sprite SRAM and palette SRAM between the Z80 and video system. Interfaces with SX28 sprite controller.

The system still utilises two SX28 microcontrollers (clocked at 64MHz) but the function of the graphics controller is now different.

SX28 #1 - Main graphics control. Originally I was using this to generate the TV frame timing but that is now handled by CPLD #2 in pure logic. This microcontroller now clocks data into CPLD #1's planar-to-chunky shift registers during the horizontal off-screen raster time, accepts the rearranged data back from the CPLD, and builds up a line of 256 4-bit pixels in its internal SRAM which it clocks out during the on screen raster time period (in sync with the sprite controller). The firmware of this microcontroller is also responsible for horizontal hardware scroll, which is merely a delay of 0 to 7 pixels when dumping out a scan line.

SX28 #2 - Sprite controller/generator. No major design changes since verison 2, just performance improvements really. Reads coordinate/definiton data from the sprite SRAM, organises it into a pre-built scanline of 256 4 bit pixels and dumps it out in sync with the background video data.

The New V3 Graphics Board - Solder Side

The graphics system uses three 5-volt async SRAM memory chips. Naturally it'd be elegant to have everything on one chip, but still..

SRAM #1 - Bitmap data: 128KB ~12ns SRAM.. Connected to CPLD #1 - Holds four banks of 32KB video data, each enough for a 16 colour 256 x 200 pixel display or four banks of two 256 8x8 16 colour characters sets and two 32x25 character maps. Needs to be high speed RAM so the SX28 can build the scan line during offscreen raster time.

SRAM #2 - Sprite data: 32KB ~12ns SRAM. . Connected to CPLD #3 - Holds upto 253 16x16 16 colour sprite definition blocks (first two blocks contain coordinate data etc) Again, needed to be fast SRAM so the SX28 could build a scanline containing at least 8 sprites in the allotted time.

SRAM #3 - Palette: 32KB ~70ns SRAM - Connected to CPLD #3 - Capacity was overkill as I'm only using 256 bytes - there was no price advantage using a smaller IC however. The background bitmap has a 16 colour palette and the sprites have a 16 colour palette (15 plus transparent) - which of course adds up to 32. However, its easy to just supply the SRAM address lines two groups of 4 bits and set the 256 colour registers to compensate - this also allows crude semi-transparent effects etc. The slower 70ns SRAM is sufficient as my pixel clock is only 125ns.

The other chips used are:

A 74HCT541 tri-state buffer to switch the Z80 databus to the sprite SRAM (single direction as the sprite SRAM is write only as far as the CPU is concerned)

74HCT245 bidirectional buffer to switch the Z80's databus to the video SRAMs (bidirectional, as the CPU needs to read and write from video memory)

74HCT574 octal latch (output buffer to an R2R resistor net colour DAC).

74HC04 hex buffer/inverter and 74HC4029 divider used to distribute an 64MHz oscillator's output to the two SX28s and divide down to 8MHz for the Z80 board and video clock.